Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs (2008)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Imprenta:
- Publisher: The Electrochemical Society
- Publisher place: Pennington
- Date published: 2008
- Source:
- Título do periódico: SBMICRO 2008: Anais
- ISSN: 1938-5862
- Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO
-
ABNT
PAVANELLO, Marcelo Antonio et al. Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs. 2008, Anais.. Pennington: The Electrochemical Society, 2008. . Acesso em: 28 abr. 2024. -
APA
Pavanello, M. A., Martino, J. A., Simoen, E., Rooyackers, R., Collaert, N., & Claeys, C. (2008). Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs. In SBMICRO 2008: Anais. Pennington: The Electrochemical Society. -
NLM
Pavanello MA, Martino JA, Simoen E, Rooyackers R, Collaert N, Claeys C. Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs. SBMICRO 2008: Anais. 2008 ;[citado 2024 abr. 28 ] -
Vancouver
Pavanello MA, Martino JA, Simoen E, Rooyackers R, Collaert N, Claeys C. Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs. SBMICRO 2008: Anais. 2008 ;[citado 2024 abr. 28 ] - Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range
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