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Artigo de periodico
Enabling HW-based task scheduling in large multicore architectures (2024)
Morais, Lucas; Álvarez, Carlos; Jiménez-González, Daniel; de Haro, Juan Miguel; Araujo , Guido ; Frank, Michael; Goldman, Alfredo ; Martorell, Xavier
Source: IEEE Transactions on Computers. Unidade: IME
Subjects: PROGRAMAÇÃO PARALELA, GEOMETRIA E MODELAGEM COMPUTACIONAL
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
MORAIS, Lucas et al. Enabling HW-based task scheduling in large multicore architectures. IEEE Transactions on Computers, v. 73, n. 1, p. 1138-151, 2024Tradução . . Disponível em: https://doi.org/10.1109/TC.2023.3323781. Acesso em: 06 jun. 2024.
APA
Morais, L., Álvarez, C., Jiménez-González, D., de Haro, J. M., Araujo , G., Frank, M., et al. (2024). Enabling HW-based task scheduling in large multicore architectures. IEEE Transactions on Computers, 73( 1), 1138-151. doi:10.1109/TC.2023.3323781
NLM
Morais L, Álvarez C, Jiménez-González D, de Haro JM, Araujo G, Frank M, Goldman A, Martorell X. Enabling HW-based task scheduling in large multicore architectures [Internet]. IEEE Transactions on Computers. 2024 ; 73( 1): 1138-151.[citado 2024 jun. 06 ] Available from: https://doi.org/10.1109/TC.2023.3323781
Vancouver
Morais L, Álvarez C, Jiménez-González D, de Haro JM, Araujo G, Frank M, Goldman A, Martorell X. Enabling HW-based task scheduling in large multicore architectures [Internet]. IEEE Transactions on Computers. 2024 ; 73( 1): 1138-151.[citado 2024 jun. 06 ] Available from: https://doi.org/10.1109/TC.2023.3323781
Artigo de periodico
Fast resource and timing aware design optimisation for high-level synthesis (2021)
Perina, André Bannwart ; Silitonga, Arthur ; Becker, Jürgen ; Bonato, Vanderlei
Source: IEEE Transactions on Computers. Unidade: ICMC
Subjects: HARDWARE, ANÁLISE DE DESEMPENHO
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PERINA, André Bannwart et al. Fast resource and timing aware design optimisation for high-level synthesis. IEEE Transactions on Computers, v. 70, n. 12, p. 2070-2082, 2021Tradução . . Disponível em: https://doi.org/10.1109/TC.2021.3112260. Acesso em: 06 jun. 2024.
APA
Perina, A. B., Silitonga, A., Becker, J., & Bonato, V. (2021). Fast resource and timing aware design optimisation for high-level synthesis. IEEE Transactions on Computers, 70( 12), 2070-2082. doi:10.1109/TC.2021.3112260
NLM
Perina AB, Silitonga A, Becker J, Bonato V. Fast resource and timing aware design optimisation for high-level synthesis [Internet]. IEEE Transactions on Computers. 2021 ; 70( 12): 2070-2082.[citado 2024 jun. 06 ] Available from: https://doi.org/10.1109/TC.2021.3112260
Vancouver
Perina AB, Silitonga A, Becker J, Bonato V. Fast resource and timing aware design optimisation for high-level synthesis [Internet]. IEEE Transactions on Computers. 2021 ; 70( 12): 2070-2082.[citado 2024 jun. 06 ] Available from: https://doi.org/10.1109/TC.2021.3112260
Artigo de periodico
Checking completeness of tests for finite state machines (2010)
Simão, Adenilso da Silva ; Petrenko, Alexandre
Source: IEEE Transactions on Computers. Unidade: ICMC
Subjects: ENGENHARIA DE SOFTWARE, SISTEMAS DE INFORMAÇÃO
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SIMÃO, Adenilso da Silva e PETRENKO, Alexandre. Checking completeness of tests for finite state machines. IEEE Transactions on Computers, v. 59, n. 8, p. 1023-1032, 2010Tradução . . Disponível em: http://ieeexplore.ieee.org/xpl/tocresult.do?isnumber=5494717. Acesso em: 06 jun. 2024.
APA
Simão, A. da S., & Petrenko, A. (2010). Checking completeness of tests for finite state machines. IEEE Transactions on Computers, 59( 8), 1023-1032. Recuperado de http://ieeexplore.ieee.org/xpl/tocresult.do?isnumber=5494717
NLM
Simão A da S, Petrenko A. Checking completeness of tests for finite state machines [Internet]. IEEE Transactions on Computers. 2010 ; 59( 8): 1023-1032.[citado 2024 jun. 06 ] Available from: http://ieeexplore.ieee.org/xpl/tocresult.do?isnumber=5494717
Vancouver
Simão A da S, Petrenko A. Checking completeness of tests for finite state machines [Internet]. IEEE Transactions on Computers. 2010 ; 59( 8): 1023-1032.[citado 2024 jun. 06 ] Available from: http://ieeexplore.ieee.org/xpl/tocresult.do?isnumber=5494717
Artigo de periodico
Remote device command and resource sharing over the Internet: a new approach based on a distributed layered architecture (2002)
Monaco, Francisco José ; Gonzaga, Adilson
Source: IEEE Transactions on Computers. Unidade: EESC
Subjects: WORLD WIDE WEB, INTERNET, TELEMÁTICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
MONACO, Francisco José e GONZAGA, Adilson. Remote device command and resource sharing over the Internet: a new approach based on a distributed layered architecture. IEEE Transactions on Computers, v. 51, n. 7, p. 787-792, 2002Tradução . . Disponível em: https://doi.org/10.1109/tc.2002.1017698. Acesso em: 06 jun. 2024.
APA
Monaco, F. J., & Gonzaga, A. (2002). Remote device command and resource sharing over the Internet: a new approach based on a distributed layered architecture. IEEE Transactions on Computers, 51( 7), 787-792. doi:10.1109/tc.2002.1017698
NLM
Monaco FJ, Gonzaga A. Remote device command and resource sharing over the Internet: a new approach based on a distributed layered architecture [Internet]. IEEE Transactions on Computers. 2002 ; 51( 7): 787-792.[citado 2024 jun. 06 ] Available from: https://doi.org/10.1109/tc.2002.1017698
Vancouver
Monaco FJ, Gonzaga A. Remote device command and resource sharing over the Internet: a new approach based on a distributed layered architecture [Internet]. IEEE Transactions on Computers. 2002 ; 51( 7): 787-792.[citado 2024 jun. 06 ] Available from: https://doi.org/10.1109/tc.2002.1017698

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