An improved model for the triangular SOI misalignment test structure (2004)
- Autores:
- Autor USP: MARTINO, JOAO ANTONIO - EP
- Unidade: EP
- Assuntos: MICROELETRÔNICA; ELETROQUÍMICA; CIRCUITOS INTEGRADOS MOS
- Idioma: Inglês
- Imprenta:
- Editora: The Electrochemical Society
- Local: Pennington
- Data de publicação: 2004
- ISBN: 1-56677-416-0
- Fonte:
- Título do periódico: Microelectronics technology and devices SBMicro 2004. Proceedings, v. 2004-03
- Nome do evento: Symposium on Microelectronics Technology and Devices SBMICRO
-
ABNT
GIACOMINI, Renato Camargo e MARTINO, João Antonio. An improved model for the triangular SOI misalignment test structure. 2004, Anais.. Pennington: The Electrochemical Society, 2004. . Acesso em: 23 abr. 2024. -
APA
Giacomini, R. C., & Martino, J. A. (2004). An improved model for the triangular SOI misalignment test structure. In Microelectronics technology and devices SBMicro 2004. Proceedings, v. 2004-03. Pennington: The Electrochemical Society. -
NLM
Giacomini RC, Martino JA. An improved model for the triangular SOI misalignment test structure. Microelectronics technology and devices SBMicro 2004. Proceedings, v. 2004-03. 2004 ;[citado 2024 abr. 23 ] -
Vancouver
Giacomini RC, Martino JA. An improved model for the triangular SOI misalignment test structure. Microelectronics technology and devices SBMicro 2004. Proceedings, v. 2004-03. 2004 ;[citado 2024 abr. 23 ] - Temperature influences on the drain leakage current behavior in graded-channel SOI nMOSFETs
- Projeto de processos de fabricação avançados aplicáveis nas tecnologias CMOS micrométricas
- Analysis of the linear kink effect in partially depleted SOI nMOSFETs
- Simple method to extract the length dependent mobility degradation factor at 77 K
- Mobility degradation influence on the SOI MOSFET channel length extraction at 77K
- Low temperature and channel engineering influence on harmonic distortion of soi nmosfets for analog applications
- Analysis of the capacitance vs. voltage in graded channel SOI capacitor
- A simple technique to reduce the influence of the series resistance on the BULK and SOI MOSFET parameter extraction
- Metodo simples para a obtencao da densidade de armadilhas na primeira e segunda interface em soi-mosfet
- Simple method for the determination of the interface trap density at 77k in fully depleted acumulation mode soi mosfets
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