Synthesis of speed-independent circuits from multi-burst graph specification and using gate-level architectures (2001)
- Authors:
- USP affiliated authors: STRUM, MARIUS - EP ; CHAU, WANG JIANG - EP
- Unidade: EP
- Assunto: CIRCUITOS INTEGRADOS VLSI
- Language: Inglês
- Imprenta:
- Source:
- Título do periódico: IBERCHIP: proceedings
- Conference titles: Workshop IBERCHIP
-
ABNT
OLIVEIRA, Duarte Lopes de et al. Synthesis of speed-independent circuits from multi-burst graph specification and using gate-level architectures. 2001, Anais.. São Paulo: ABINEE, 2001. . Acesso em: 24 abr. 2024. -
APA
Oliveira, D. L. de, Strum, M., Wang, J. C., & Cunha, W. C. (2001). Synthesis of speed-independent circuits from multi-burst graph specification and using gate-level architectures. In IBERCHIP: proceedings. São Paulo: ABINEE. -
NLM
Oliveira DL de, Strum M, Wang JC, Cunha WC. Synthesis of speed-independent circuits from multi-burst graph specification and using gate-level architectures. IBERCHIP: proceedings. 2001 ;[citado 2024 abr. 24 ] -
Vancouver
Oliveira DL de, Strum M, Wang JC, Cunha WC. Synthesis of speed-independent circuits from multi-burst graph specification and using gate-level architectures. IBERCHIP: proceedings. 2001 ;[citado 2024 abr. 24 ] - Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers
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