Analog performance of graded-channel SOI NMOSFETS at low temperatures (2002)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Imprenta:
- Publisher: The Electrochemical Society
- Publisher place: Pennington
- Date published: 2002
- Source:
- Título do periódico: Microelectronics Technology and Devices SBMICRO 2002
- Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO
-
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e FLANDRE, Denis. Analog performance of graded-channel SOI NMOSFETS at low temperatures. Microelectronics Technology and Devices SBMICRO 2002. Tradução . Pennington: The Electrochemical Society, 2002. . . Acesso em: 24 abr. 2024. -
APA
Pavanello, M. A., Martino, J. A., & Flandre, D. (2002). Analog performance of graded-channel SOI NMOSFETS at low temperatures. In Microelectronics Technology and Devices SBMICRO 2002. Pennington: The Electrochemical Society. -
NLM
Pavanello MA, Martino JA, Flandre D. Analog performance of graded-channel SOI NMOSFETS at low temperatures. In: Microelectronics Technology and Devices SBMICRO 2002. Pennington: The Electrochemical Society; 2002. [citado 2024 abr. 24 ] -
Vancouver
Pavanello MA, Martino JA, Flandre D. Analog performance of graded-channel SOI NMOSFETS at low temperatures. In: Microelectronics Technology and Devices SBMICRO 2002. Pennington: The Electrochemical Society; 2002. [citado 2024 abr. 24 ] - Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range
- Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures
- Comparison between conventional and graded-channel SOI nMOSFETs in low temperature operation
- Impact of the graded-channel architecture on double gate transistors for high-performance analog applications
- Comparison between 0.13Mm partially-depleted silicon-on-insulator technology with floating body operation at 300 K and 90 K
- Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments
- Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures
- Design of operational transconductance amplifiers with improved gain by using graded-channel SOI nMOSFETs
- Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation
- Analysis of HALO implant influence on the self-heating and self-heating enhanced impact ionization on 0.13 Mm floating-body partially-depleted SOI MOSFET at low temperature
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