A benchmark approach for compilers in reconfigurable hardware (2006)
- Authors:
- Autor USP: SILVA, JORGE LUIZ E - ICMC
- Unidade: ICMC
- Subjects: SISTEMAS DISTRIBUÍDOS; PROGRAMAÇÃO CONCORRENTE
- Language: Inglês
- Conference titles: International Workshop on System-on-Chip
-
ABNT
LOPES, Joelmir José e SILVA, Jorge Luiz e. A benchmark approach for compilers in reconfigurable hardware. 2006, Anais.. [S.l.]: Instituto de Ciências Matemáticas e de Computação, Universidade de São Paulo, 2006. . Acesso em: 11 maio 2024. -
APA
Lopes, J. J., & Silva, J. L. e. (2006). A benchmark approach for compilers in reconfigurable hardware. In . Instituto de Ciências Matemáticas e de Computação, Universidade de São Paulo. -
NLM
Lopes JJ, Silva JL e. A benchmark approach for compilers in reconfigurable hardware. 2006 ;[citado 2024 maio 11 ] -
Vancouver
Lopes JJ, Silva JL e. A benchmark approach for compilers in reconfigurable hardware. 2006 ;[citado 2024 maio 11 ] - Research and partial analysis of overhead of a partition model for a partially reconfigurable hardware in a data-driven machine-chicflow
- A partition model using partial reconfigurable hardware for chipCflow project
- Tag management in a reconfigurable tagged-token dataflow architecture
- A dynamic dataflow architecture using partial reconfigurable hardware as an option for multiple cores
- Execution of algorithms using a dynamic dataflow model for reconfigurable hardware: a purpose for matching data
- RtrASSoc51 - adaptable superscalar reconfigurable programmable system on chip: the reconfigurable tools for DSR a development system
- C commands Implemented direct into the hardware using the ChipCflow Machine
- RtrASSoc51-rI2C (reconfigurable inter integrated circuit)
- The ChipCflow: a tool to generate hardware accelerators using a static dataflow machine designed for a FPGA
- Execution of algorithms using a dynamic dataflow model for reconfigurable hardware: commands in dataflow graph
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