Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs (2015)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; AGOPIAN, PAULA GHEDINI DER - EP
- Unidade: EP
- DOI: 10.1016/j.sse.2014.07.010
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Source:
- Título do periódico: Solid-State Electronics
- Volume/Número/Paginação/Ano: v.103, p. 209-215, Jan 2015
- Este periódico é de assinatura
- Este artigo NÃO é de acesso aberto
- Cor do Acesso Aberto: closed
-
ABNT
BÜHLER, Rudolf Theoderich et al. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs. Solid-State Electronics, v. 103, p. 209-215, 2015Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2014.07.010. Acesso em: 19 abr. 2024. -
APA
Bühler, R. T., Agopian, P. G. D., Collaert, N., Simoen, E., Claeys, C., & Martino, J. A. (2015). Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs. Solid-State Electronics, 103, 209-215. doi:10.1016/j.sse.2014.07.010 -
NLM
Bühler RT, Agopian PGD, Collaert N, Simoen E, Claeys C, Martino JA. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs [Internet]. Solid-State Electronics. 2015 ;103 209-215.[citado 2024 abr. 19 ] Available from: https://doi.org/10.1016/j.sse.2014.07.010 -
Vancouver
Bühler RT, Agopian PGD, Collaert N, Simoen E, Claeys C, Martino JA. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs [Internet]. Solid-State Electronics. 2015 ;103 209-215.[citado 2024 abr. 19 ] Available from: https://doi.org/10.1016/j.sse.2014.07.010 - Influence of interface trap density on vertical NW-TFETs with different source composition
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- Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source
- Experimental comparison between tensile and compressive uniaxially stressed MuGFETs under X-ray radiation
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- Study of line-TFET analog performance comparing with other TFET and MOSFET architectures
- Stress engineering and proton radiation influence on off-state leakage current in triple-gate SOI devices
- Experimental Comparison Between Trigate p-TFET and p-FinFET Analog Performance as a Function of Temperature
- Influence of the Source Composition on the Analog Performance Parameters of Vertical Nanowire-TFETs
Informações sobre o DOI: 10.1016/j.sse.2014.07.010 (Fonte: oaDOI API)
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