Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures (2016)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; AGOPIAN, PAULA GHEDINI DER - EP ; MARTINO, MARCIO DALLA VALLE - EP
- Unidade: EP
- DOI: 10.1088/0268-1242/31/5/055001
- Assunto: SEMICONDUTORES
- Language: Inglês
- Source:
- Título do periódico: Semiconductor Science and Technology
- Volume/Número/Paginação/Ano: v. 31, n. 5, 055001, 2016
- Este periódico é de assinatura
- Este artigo NÃO é de acesso aberto
- Cor do Acesso Aberto: closed
-
ABNT
MARTINO, Márcio Dalla Valle et al. Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures. Semiconductor Science and Technology, v. 31, n. 5, 2016Tradução . . Disponível em: https://doi.org/10.1088/0268-1242/31/5/055001. Acesso em: 24 abr. 2024. -
APA
Martino, M. D. V., Martino, J. A., Agopian, P. G. D., Vandooren, A., Rooyackers, R., Simoen, E., & Claeys, C. (2016). Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures. Semiconductor Science and Technology, 31( 5). doi:10.1088/0268-1242/31/5/055001 -
NLM
Martino MDV, Martino JA, Agopian PGD, Vandooren A, Rooyackers R, Simoen E, Claeys C. Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures [Internet]. Semiconductor Science and Technology. 2016 ; 31( 5):[citado 2024 abr. 24 ] Available from: https://doi.org/10.1088/0268-1242/31/5/055001 -
Vancouver
Martino MDV, Martino JA, Agopian PGD, Vandooren A, Rooyackers R, Simoen E, Claeys C. Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures [Internet]. Semiconductor Science and Technology. 2016 ; 31( 5):[citado 2024 abr. 24 ] Available from: https://doi.org/10.1088/0268-1242/31/5/055001 - Performance of differential pair circuits designed with line tunnel FET devices at different temperatures
- Nanowire Tunnel Field Effect Transistors at High Temperature
- Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism
- Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures
- Influence of interface trap density on vertical NW-TFETs with different source composition
- Temperature influence on nanowire tunnel field effect transistors
- Cross-section features influence on surrounding MuGFETs
- Threshold voltage extraction in Tunnel FETs
- Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source
- Experimental comparison between tensile and compressive uniaxially stressed MuGFETs under X-ray radiation
Informações sobre o DOI: 10.1088/0268-1242/31/5/055001 (Fonte: oaDOI API)
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