Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation (2016)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; SONNENBERG, VICTOR - EP ; ITOCAZU, VITOR TATSUO - EP ; SASAKI, KATIA REGINA AKEMI - EP
- Unidade: EP
- DOI: 10.29292/jics.v12i2.458
- Assunto: SEMICONDUTORES
- Language: Inglês
- Source:
- Título do periódico: Journal of Integrated Circuits and Systems
- Volume/Número/Paginação/Ano: v. 12, n. 2, p.101-106, Aug 2016
- Este periódico é de acesso aberto
- Este artigo é de acesso aberto
- URL de acesso aberto
- Cor do Acesso Aberto: gold
-
ABNT
ITOCAZU, Vitor Tatsuo et al. Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation. Journal of Integrated Circuits and Systems, v. 12, n. 2, p. 101-106, 2016Tradução . . Disponível em: https://doi.org/10.29292/jics.v12i2.458. Acesso em: 23 abr. 2024. -
APA
Itocazu, V. T., Martino, J. A., Sasaki, K. R. A., Simoen, E., Claeys, C., & Sonnenberg, V. (2016). Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation. Journal of Integrated Circuits and Systems, 12( 2), 101-106. doi:10.29292/jics.v12i2.458 -
NLM
Itocazu VT, Martino JA, Sasaki KRA, Simoen E, Claeys C, Sonnenberg V. Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation [Internet]. Journal of Integrated Circuits and Systems. 2016 ; 12( 2): 101-106.[citado 2024 abr. 23 ] Available from: https://doi.org/10.29292/jics.v12i2.458 -
Vancouver
Itocazu VT, Martino JA, Sasaki KRA, Simoen E, Claeys C, Sonnenberg V. Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation [Internet]. Journal of Integrated Circuits and Systems. 2016 ; 12( 2): 101-106.[citado 2024 abr. 23 ] Available from: https://doi.org/10.29292/jics.v12i2.458 - Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies
- Analysis of the silicon film thickness and the ground plane influence on ultra thin buried oxide SOI nMOSFETs.
- Corner effect on capacitance-voltage curves in triple gate FinFET
- Optimizing the front and back biases for the best sense margin and retention time in UTBOX FBRAM
- Enhanced dynamic threshold voltage UTBB SOI nMOSFETs
- Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View
- Impact of the extension region concentration on the UTBOX IT-FBRAM
- Experimental and Simulation of 1T-DRAM Trend with the Gate Length on UTBOX Devices
- Efeito do substrato em transistores SOI de camada de silício e óxido enterrado ultrafinos
- Propostas de melhorias de desempenho de célula de memória dinâmica utilizando um único transistor UTBOX SOI
Informações sobre o DOI: 10.29292/jics.v12i2.458 (Fonte: oaDOI API)
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