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Artigo de periodico
Experimental study of MISHEMT from 450 K down to 200 K for analog applications (2023)
Perina, Welder Fernandes; Martino, João Antonio ; Simoen, Eddy ; Peralagu, Uthayasankaran; Collaert, Nadine ; Agopian, Paula Ghedini Der
Source: Solid State Electronics. Unidade: EP
Subjects: TRANSISTORES, CIRCUITOS ANALÓGICOS, SEMICONDUTORES
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ABNT
PERINA, Welder Fernandes et al. Experimental study of MISHEMT from 450 K down to 200 K for analog applications. Solid State Electronics, v. 208, p. 1-4, 2023Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2023.108742. Acesso em: 23 maio 2024.
APA
Perina, W. F., Martino, J. A., Simoen, E., Peralagu, U., Collaert, N., & Agopian, P. G. D. (2023). Experimental study of MISHEMT from 450 K down to 200 K for analog applications. Solid State Electronics, 208, 1-4. doi:10.1016/j.sse.2023.108742
NLM
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Experimental study of MISHEMT from 450 K down to 200 K for analog applications [Internet]. Solid State Electronics. 2023 ; 208 1-4.[citado 2024 maio 23 ] Available from: https://doi.org/10.1016/j.sse.2023.108742
Vancouver
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Experimental study of MISHEMT from 450 K down to 200 K for analog applications [Internet]. Solid State Electronics. 2023 ; 208 1-4.[citado 2024 maio 23 ] Available from: https://doi.org/10.1016/j.sse.2023.108742
Artigo de periodico
Experimental study of MISHEMT from 450k down to 200 k for analog applications (2023)
Perina, Welder Fernandes; Martino, João Antonio ; Simoen, Eddy ; Peralagu, Uthayasankaran; Collaert, Nadine ; Agopian, Paula Ghedini Der
Source: Solid State Electronics. Unidade: EP
Subjects: TRANSISTORES, CIRCUITOS ANALÓGICOS, TEMPERATURA
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ABNT
PERINA, Welder Fernandes et al. Experimental study of MISHEMT from 450k down to 200 k for analog applications. Solid State Electronics, v. 208, p. 1-4, 2023Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2023.108742. Acesso em: 23 maio 2024.
APA
Perina, W. F., Martino, J. A., Simoen, E., Peralagu, U., Collaert, N., & Agopian, P. G. D. (2023). Experimental study of MISHEMT from 450k down to 200 k for analog applications. Solid State Electronics, 208, 1-4. doi:10.1016/j.sse.2023.108742
NLM
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Experimental study of MISHEMT from 450k down to 200 k for analog applications [Internet]. Solid State Electronics. 2023 ; 208 1-4.[citado 2024 maio 23 ] Available from: https://doi.org/10.1016/j.sse.2023.108742
Vancouver
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Experimental study of MISHEMT from 450k down to 200 k for analog applications [Internet]. Solid State Electronics. 2023 ; 208 1-4.[citado 2024 maio 23 ] Available from: https://doi.org/10.1016/j.sse.2023.108742
Trabalho de evento
Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K (2023)
Perina, Welder Fernandes; Martino, João Antonio ; Simoen, Eddy ; Peralagu, Uthayasankaran; Collaert, Nadine ; Agopian, Paula Ghedini Der
Source: SBMicro. Conference titles: Symposium on Microelectronics Technology and Devices. Unidade: EP
Subjects: TRANSISTORES, SEMICONDUTORES
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ABNT
PERINA, Welder Fernandes et al. Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K. 2023, Anais.. [Piscataway, N.J.]: IEEE, 2023. Disponível em: https://doi.org/10.1109/SBMicro60499.2023.10302604. Acesso em: 23 maio 2024.
APA
Perina, W. F., Martino, J. A., Simoen, E., Peralagu, U., Collaert, N., & Agopian, P. G. D. (2023). Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K. In SBMicro. [Piscataway, N.J.]: IEEE. doi:10.1109/SBMicro60499.2023.10302604
NLM
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K [Internet]. SBMicro. 2023 ;[citado 2024 maio 23 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302604
Vancouver
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K [Internet]. SBMicro. 2023 ;[citado 2024 maio 23 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302604
Artigo de periodico
MISHEMT intrinsic voltage gain under multiple channel output characteristics (2023)
Canales, Bruno Godoy; Perina, Welder Fernandes; Martino, João Antonio ; Simoen, Eddy ; Peralagu, Uthayasankaran; Collaert, Nadine ; Agopian, Paula Ghedini Der
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: TRANSISTORES, SEMICONDUTORES
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ABNT
CANALES, Bruno Godoy et al. MISHEMT intrinsic voltage gain under multiple channel output characteristics. Semiconductor Science and Technology, v. 38, n. 11, p. 1-6, 2023Tradução . . Disponível em: https://doi.org/10.1088/1361-6641/acfa1f. Acesso em: 23 maio 2024.
APA
Canales, B. G., Perina, W. F., Martino, J. A., Simoen, E., Peralagu, U., Collaert, N., & Agopian, P. G. D. (2023). MISHEMT intrinsic voltage gain under multiple channel output characteristics. Semiconductor Science and Technology, 38( 11), 1-6. doi:10.1088/1361-6641/acfa1f
NLM
Canales BG, Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. MISHEMT intrinsic voltage gain under multiple channel output characteristics [Internet]. Semiconductor Science and Technology. 2023 ; 38( 11): 1-6.[citado 2024 maio 23 ] Available from: https://doi.org/10.1088/1361-6641/acfa1f
Vancouver
Canales BG, Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. MISHEMT intrinsic voltage gain under multiple channel output characteristics [Internet]. Semiconductor Science and Technology. 2023 ; 38( 11): 1-6.[citado 2024 maio 23 ] Available from: https://doi.org/10.1088/1361-6641/acfa1f
Artigo de periodico
The impact of the temperature on In0.53Ga0.47As nTFETs (2018)
Bordallo, Caio Cesar Mendes ; Mocuta, Dan; Collaert, Nadine ; Alian, A; Simoen, Eddy ; Claeys, Cor ; Agopian, Paula Ghedini Der ; Martino, João Antonio ; Rooyackers, Rita; Mols, Yannick; Van Dooren, A; Verhulst, Anne S; Lin, D
Source: Composants nanoélectroniques. Unidade: EP
Assunto: SEMICONDUTORES
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ABNT
BORDALLO, Caio Cesar Mendes et al. The impact of the temperature on In0.53Ga0.47As nTFETs. Composants nanoélectroniques, v. 18, n. 1, 2018Tradução . . Disponível em: https://doi.org/10.21494/iste.op.2018.0224. Acesso em: 23 maio 2024.
APA
Bordallo, C. C. M., Mocuta, D., Collaert, N., Alian, A., Simoen, E., Claeys, C., et al. (2018). The impact of the temperature on In0.53Ga0.47As nTFETs. Composants nanoélectroniques, 18( 1). doi:10.21494/iste.op.2018.0224
NLM
Bordallo CCM, Mocuta D, Collaert N, Alian A, Simoen E, Claeys C, Agopian PGD, Martino JA, Rooyackers R, Mols Y, Van Dooren A, Verhulst AS, Lin D. The impact of the temperature on In0.53Ga0.47As nTFETs [Internet]. Composants nanoélectroniques. 2018 ;18( 1):[citado 2024 maio 23 ] Available from: https://doi.org/10.21494/iste.op.2018.0224
Vancouver
Bordallo CCM, Mocuta D, Collaert N, Alian A, Simoen E, Claeys C, Agopian PGD, Martino JA, Rooyackers R, Mols Y, Van Dooren A, Verhulst AS, Lin D. The impact of the temperature on In0.53Ga0.47As nTFETs [Internet]. Composants nanoélectroniques. 2018 ;18( 1):[citado 2024 maio 23 ] Available from: https://doi.org/10.21494/iste.op.2018.0224
Artigo de periodico
The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs (2017)
Bordallo, Caio Cesar Mendes ; Collaert, Nadine ; Claeys, Cor ; Simoen, Eddy ; Vandooren, A; Rooyackers, Rita; Mols, Yannick; Alian, A; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: IEEE Transactions on Electron Devices. Unidade: EP
Subjects: MICROELETRÔNICA, SEMICONDUTORES
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ABNT
BORDALLO, Caio Cesar Mendes et al. The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs. IEEE Transactions on Electron Devices, v. 64, n. 9, p. 3595-3600, 2017Tradução . . Disponível em: https://doi.org/10.1109/ted.2017.2721110. Acesso em: 23 maio 2024.
APA
Bordallo, C. C. M., Collaert, N., Claeys, C., Simoen, E., Vandooren, A., Rooyackers, R., et al. (2017). The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs. IEEE Transactions on Electron Devices, 64( 9), 3595-3600. doi:10.1109/ted.2017.2721110
NLM
Bordallo CCM, Collaert N, Claeys C, Simoen E, Vandooren A, Rooyackers R, Mols Y, Alian A, Agopian PGD, Martino JA. The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs [Internet]. IEEE Transactions on Electron Devices. 2017 ; 64( 9): 3595-3600.[citado 2024 maio 23 ] Available from: https://doi.org/10.1109/ted.2017.2721110
Vancouver
Bordallo CCM, Collaert N, Claeys C, Simoen E, Vandooren A, Rooyackers R, Mols Y, Alian A, Agopian PGD, Martino JA. The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs [Internet]. IEEE Transactions on Electron Devices. 2017 ; 64( 9): 3595-3600.[citado 2024 maio 23 ] Available from: https://doi.org/10.1109/ted.2017.2721110
Artigo de periodico
Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes (2016)
Oliveira, Alberto Vinicius de; Agopian, Paula Ghedini Der ; Simoen, Eddy ; Langer, Robert; Collaert, Nadine ; Thean, Aaron; Claeys, Cor ; Martino, João Antonio
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: SEMICONDUTORES, MICROELETRÔNICA
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ABNT
OLIVEIRA, Alberto Vinicius de et al. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes. Semiconductor Science and Technology, v. 31, n. 11, p. 114002 , 2016Tradução . . Disponível em: https://doi.org/10.1088/0268-1242/31/11/114002. Acesso em: 23 maio 2024.
APA
Oliveira, A. V. de, Agopian, P. G. D., Simoen, E., Langer, R., Collaert, N., Thean, A., et al. (2016). Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes. Semiconductor Science and Technology, 31( 11), 114002 . doi:10.1088/0268-1242/31/11/114002
NLM
Oliveira AV de, Agopian PGD, Simoen E, Langer R, Collaert N, Thean A, Claeys C, Martino JA. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114002 .[citado 2024 maio 23 ] Available from: https://doi.org/10.1088/0268-1242/31/11/114002
Vancouver
Oliveira AV de, Agopian PGD, Simoen E, Langer R, Collaert N, Thean A, Claeys C, Martino JA. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114002 .[citado 2024 maio 23 ] Available from: https://doi.org/10.1088/0268-1242/31/11/114002
Artigo de periodico
Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs (2016)
Oliveira, Alberto Vinicius de; Simoen, Eddy ; Thean, Aaron; Agopian, Paula Ghedini Der ; Martino, João Antonio ; Claeys, Cor ; Mertens, Hans; Collaert, Nadine
Source: ECS Transactions volume 66 issue 5 on pages 309 to 314. Unidade: EP
Subjects: MICROELETRÔNICA, TRANSISTORES
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ABNT
OLIVEIRA, Alberto Vinicius de et al. Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs. ECS Transactions volume 66 issue 5 on pages 309 to 314, v. 66, n. 5, p. 309-314, 2016Tradução . . Disponível em: https://doi.org/10.1149/06605.0309ecst. Acesso em: 23 maio 2024.
APA
Oliveira, A. V. de, Simoen, E., Thean, A., Agopian, P. G. D., Martino, J. A., Claeys, C., et al. (2016). Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs. ECS Transactions volume 66 issue 5 on pages 309 to 314, 66( 5), 309-314. doi:10.1149/06605.0309ecst
NLM
Oliveira AV de, Simoen E, Thean A, Agopian PGD, Martino JA, Claeys C, Mertens H, Collaert N. Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs [Internet]. ECS Transactions volume 66 issue 5 on pages 309 to 314. 2016 ; 66( 5): 309-314.[citado 2024 maio 23 ] Available from: https://doi.org/10.1149/06605.0309ecst
Vancouver
Oliveira AV de, Simoen E, Thean A, Agopian PGD, Martino JA, Claeys C, Mertens H, Collaert N. Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs [Internet]. ECS Transactions volume 66 issue 5 on pages 309 to 314. 2016 ; 66( 5): 309-314.[citado 2024 maio 23 ] Available from: https://doi.org/10.1149/06605.0309ecst
Artigo de periodico
Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures (2016)
Oliveira, Alberto Vinicius de; Collaert, Nadine ; Thean, Aaron; Claeys, Cor ; Simoen, Eddy ; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Subjects: SEMICONDUTORES, MICROELETRÔNICA
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ABNT
OLIVEIRA, Alberto Vinicius de et al. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures. Solid-State Electronics, v. 123, p. 124-129, 2016Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2016.05.004. Acesso em: 23 maio 2024.
APA
Oliveira, A. V. de, Collaert, N., Thean, A., Claeys, C., Simoen, E., Agopian, P. G. D., & Martino, J. A. (2016). Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures. Solid-State Electronics, 123, 124-129. doi:10.1016/j.sse.2016.05.004
NLM
Oliveira AV de, Collaert N, Thean A, Claeys C, Simoen E, Agopian PGD, Martino JA. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures [Internet]. Solid-State Electronics. 2016 ; 123 124-129.[citado 2024 maio 23 ] Available from: https://doi.org/10.1016/j.sse.2016.05.004
Vancouver
Oliveira AV de, Collaert N, Thean A, Claeys C, Simoen E, Agopian PGD, Martino JA. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures [Internet]. Solid-State Electronics. 2016 ; 123 124-129.[citado 2024 maio 23 ] Available from: https://doi.org/10.1016/j.sse.2016.05.004
Artigo de periodico
Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs (2015)
Bühler, Rudolf Theoderich; Agopian, Paula Ghedini Der ; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Solid-State Electronics. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
BÜHLER, Rudolf Theoderich et al. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs. Solid-State Electronics, v. 103, p. 209-215, 2015Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2014.07.010. Acesso em: 23 maio 2024.
APA
Bühler, R. T., Agopian, P. G. D., Collaert, N., Simoen, E., Claeys, C., & Martino, J. A. (2015). Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs. Solid-State Electronics, 103, 209-215. doi:10.1016/j.sse.2014.07.010
NLM
Bühler RT, Agopian PGD, Collaert N, Simoen E, Claeys C, Martino JA. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs [Internet]. Solid-State Electronics. 2015 ;103 209-215.[citado 2024 maio 23 ] Available from: https://doi.org/10.1016/j.sse.2014.07.010
Vancouver
Bühler RT, Agopian PGD, Collaert N, Simoen E, Claeys C, Martino JA. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs [Internet]. Solid-State Electronics. 2015 ;103 209-215.[citado 2024 maio 23 ] Available from: https://doi.org/10.1016/j.sse.2014.07.010
Artigo de periodico
Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation (2014)
Caño de Andrade, Maria Glória; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Aoulaiche, Marc; Martino, João Antonio
Source: Microelectronics Reliability. Unidade: EP
Subjects: SILÍCIO, MICROELETRÔNICA
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ABNT
CAÑO DE ANDRADE, Maria Glória et al. Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation. Microelectronics Reliability, v. 54, n. 11, p. 2349-2354, 2014Tradução . . Disponível em: https://doi.org/10.1016/j.microrel.2014.06.013. Acesso em: 23 maio 2024.
APA
Caño de Andrade, M. G., Collaert, N., Simoen, E., Claeys, C., Aoulaiche, M., & Martino, J. A. (2014). Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation. Microelectronics Reliability, 54( 11), 2349-2354. doi:10.1016/j.microrel.2014.06.013
NLM
Caño de Andrade MG, Collaert N, Simoen E, Claeys C, Aoulaiche M, Martino JA. Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation [Internet]. Microelectronics Reliability. 2014 ; 54( 11): 2349-2354.[citado 2024 maio 23 ] Available from: https://doi.org/10.1016/j.microrel.2014.06.013
Vancouver
Caño de Andrade MG, Collaert N, Simoen E, Claeys C, Aoulaiche M, Martino JA. Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation [Internet]. Microelectronics Reliability. 2014 ; 54( 11): 2349-2354.[citado 2024 maio 23 ] Available from: https://doi.org/10.1016/j.microrel.2014.06.013
Artigo de periodico
Optimizing the front and back biases for the best sense margin and retention time in UTBOX FBRAM (2013)
Almeida, Luciano Mendes; Sasaki, Kátia Regina Akemi; Caillat, Christian; Aoulaiche, Marc; Collaert, Nadine ; Jurczak, Malgorzata; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Solid-State Electronics Volume 90, December 2013, Pages 149-154. Unidade: EP
Assunto: SIMULAÇÃO
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ABNT
ALMEIDA, Luciano Mendes et al. Optimizing the front and back biases for the best sense margin and retention time in UTBOX FBRAM. Solid-State Electronics Volume 90, December 2013, Pages 149-154, v. 90, p. 149-154, 2013Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2013.02.038. Acesso em: 23 maio 2024.
APA
Almeida, L. M., Sasaki, K. R. A., Caillat, C., Aoulaiche, M., Collaert, N., Jurczak, M., et al. (2013). Optimizing the front and back biases for the best sense margin and retention time in UTBOX FBRAM. Solid-State Electronics Volume 90, December 2013, Pages 149-154, 90, 149-154. doi:10.1016/j.sse.2013.02.038
NLM
Almeida LM, Sasaki KRA, Caillat C, Aoulaiche M, Collaert N, Jurczak M, Simoen E, Claeys C, Martino JA. Optimizing the front and back biases for the best sense margin and retention time in UTBOX FBRAM [Internet]. Solid-State Electronics Volume 90, December 2013, Pages 149-154. 2013 ; 90 149-154.[citado 2024 maio 23 ] Available from: https://doi.org/10.1016/j.sse.2013.02.038
Vancouver
Almeida LM, Sasaki KRA, Caillat C, Aoulaiche M, Collaert N, Jurczak M, Simoen E, Claeys C, Martino JA. Optimizing the front and back biases for the best sense margin and retention time in UTBOX FBRAM [Internet]. Solid-State Electronics Volume 90, December 2013, Pages 149-154. 2013 ; 90 149-154.[citado 2024 maio 23 ] Available from: https://doi.org/10.1016/j.sse.2013.02.038
Trabalho de evento
Low-Frequency noise behaviour of bulk and DTMOS triple-gate devices under 60 MeV proton irradiaton (2012)
Caño de Andrade, Maria Glória; Martino, João Antonio ; Aoulaiche, Marc; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor
Source: Proceedings of the conference. Conference titles: International Conference on Ultimate Integration on Silicon. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
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ABNT
CAÑO DE ANDRADE, Maria Glória et al. Low-Frequency noise behaviour of bulk and DTMOS triple-gate devices under 60 MeV proton irradiaton. 2012, Anais.. Piscataway: IEEE, 2012. . Acesso em: 23 maio 2024.
APA
Caño de Andrade, M. G., Martino, J. A., Aoulaiche, M., Collaert, N., Simoen, E., & Claeys, C. (2012). Low-Frequency noise behaviour of bulk and DTMOS triple-gate devices under 60 MeV proton irradiaton. In Proceedings of the conference. Piscataway: IEEE.
NLM
Caño de Andrade MG, Martino JA, Aoulaiche M, Collaert N, Simoen E, Claeys C. Low-Frequency noise behaviour of bulk and DTMOS triple-gate devices under 60 MeV proton irradiaton. Proceedings of the conference. 2012 ;[citado 2024 maio 23 ]
Vancouver
Caño de Andrade MG, Martino JA, Aoulaiche M, Collaert N, Simoen E, Claeys C. Low-Frequency noise behaviour of bulk and DTMOS triple-gate devices under 60 MeV proton irradiaton. Proceedings of the conference. 2012 ;[citado 2024 maio 23 ]
Trabalho de evento
Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices (2012)
Almeida, Luciano Mendes; Martino, João Antonio ; Aoulaiche, Marc; Sasaki, Kátia Regina Akemi; Nicoletti, Talitha; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Jurczak, Michael J
Source: Proceedings of the conference. Conference titles: International Conference on Ultimate Integration on Silicon. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ALMEIDA, Luciano Mendes et al. Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices. 2012, Anais.. Piscataway: IEEE, 2012. Disponível em: https://doi.org/10.1109/ULIS.2012.6193357. Acesso em: 23 maio 2024.
APA
Almeida, L. M., Martino, J. A., Aoulaiche, M., Sasaki, K. R. A., Nicoletti, T., Collaert, N., et al. (2012). Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices. In Proceedings of the conference. Piscataway: IEEE. doi:10.1109/ULIS.2012.6193357
NLM
Almeida LM, Martino JA, Aoulaiche M, Sasaki KRA, Nicoletti T, Collaert N, Simoen E, Claeys C, Jurczak MJ. Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices [Internet]. Proceedings of the conference. 2012 ;[citado 2024 maio 23 ] Available from: https://doi.org/10.1109/ULIS.2012.6193357
Vancouver
Almeida LM, Martino JA, Aoulaiche M, Sasaki KRA, Nicoletti T, Collaert N, Simoen E, Claeys C, Jurczak MJ. Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices [Internet]. Proceedings of the conference. 2012 ;[citado 2024 maio 23 ] Available from: https://doi.org/10.1109/ULIS.2012.6193357
Trabalho de evento
UTBOX SOI devices with high-k gate dielectric under analog performance (2012)
Galeti, Milene; Rodrigues, Michele; Aoulaiche, Marc; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
GALETI, Milene et al. UTBOX SOI devices with high-k gate dielectric under analog performance. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0119ecst. Acesso em: 23 maio 2024.
APA
Galeti, M., Rodrigues, M., Aoulaiche, M., Collaert, N., Simoen, E., Claeys, C., & Martino, J. A. (2012). UTBOX SOI devices with high-k gate dielectric under analog performance. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0119ecst
NLM
Galeti M, Rodrigues M, Aoulaiche M, Collaert N, Simoen E, Claeys C, Martino JA. UTBOX SOI devices with high-k gate dielectric under analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 23 ] Available from: https://doi.org/10.1149/04901.0119ecst
Vancouver
Galeti M, Rodrigues M, Aoulaiche M, Collaert N, Simoen E, Claeys C, Martino JA. UTBOX SOI devices with high-k gate dielectric under analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 23 ] Available from: https://doi.org/10.1149/04901.0119ecst
Artigo de periodico
Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs (2010)
Rodrigues, M.; Martino, João Antonio ; Mercha, A.; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor
Source: Solid-State Electronics. Unidade: EP
Subjects: TRANSISTORES, ELETRODO
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
RODRIGUES, M. et al. Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs. Solid-State Electronics, v. 54, n. 12, p. 1592-1597, 2010Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2010.07.007. Acesso em: 23 maio 2024.
APA
Rodrigues, M., Martino, J. A., Mercha, A., Collaert, N., Simoen, E., & Claeys, C. (2010). Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs. Solid-State Electronics, 54( 12), 1592-1597. doi:10.1016/j.sse.2010.07.007
NLM
Rodrigues M, Martino JA, Mercha A, Collaert N, Simoen E, Claeys C. Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs [Internet]. Solid-State Electronics. 2010 ;54( 12): 1592-1597.[citado 2024 maio 23 ] Available from: https://doi.org/10.1016/j.sse.2010.07.007
Vancouver
Rodrigues M, Martino JA, Mercha A, Collaert N, Simoen E, Claeys C. Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs [Internet]. Solid-State Electronics. 2010 ;54( 12): 1592-1597.[citado 2024 maio 23 ] Available from: https://doi.org/10.1016/j.sse.2010.07.007
Artigo de periodico
Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs (2010)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor ; Rooyackers, Rita; Collaert, Nadine
Source: Journal of Integrated Circuits and Systems. Unidade: EP
Assunto: TRANSISTORES
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs. Journal of Integrated Circuits and Systems, v. 5, n. 2, p. 168-173, 2010Tradução . . Disponível em: https://doi.org/10.29292/jics.v5i2.324. Acesso em: 23 maio 2024.
APA
Pavanello, M. A., Martino, J. A., Simoen, E., Claeys, C., Rooyackers, R., & Collaert, N. (2010). Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs. Journal of Integrated Circuits and Systems, 5( 2), 168-173. doi:10.29292/jics.v5i2.324
NLM
Pavanello MA, Martino JA, Simoen E, Claeys C, Rooyackers R, Collaert N. Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs [Internet]. Journal of Integrated Circuits and Systems. 2010 ;5( 2): 168-173.[citado 2024 maio 23 ] Available from: https://doi.org/10.29292/jics.v5i2.324
Vancouver
Pavanello MA, Martino JA, Simoen E, Claeys C, Rooyackers R, Collaert N. Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs [Internet]. Journal of Integrated Circuits and Systems. 2010 ;5( 2): 168-173.[citado 2024 maio 23 ] Available from: https://doi.org/10.29292/jics.v5i2.324
Artigo de periodico
Analog performance of SOI nFinFETs with different TiN gate electrode thickness (2010)
Galeti, Milene; Rodrigues, Michele; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Microelectronics Technology and Devices - SBMicro 2010. Unidade: EP
Assunto: TRANSISTORES
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
GALETI, Milene et al. Analog performance of SOI nFinFETs with different TiN gate electrode thickness. Microelectronics Technology and Devices - SBMicro 2010, v. 31, n. 1, p. 59-65, 2010Tradução . . Disponível em: https://doi.org/10.1149/1.3474142. Acesso em: 23 maio 2024.
APA
Galeti, M., Rodrigues, M., Collaert, N., Simoen, E., Claeys, C., & Martino, J. A. (2010). Analog performance of SOI nFinFETs with different TiN gate electrode thickness. Microelectronics Technology and Devices - SBMicro 2010, 31( 1), 59-65. doi:10.1149/1.3474142
NLM
Galeti M, Rodrigues M, Collaert N, Simoen E, Claeys C, Martino JA. Analog performance of SOI nFinFETs with different TiN gate electrode thickness [Internet]. Microelectronics Technology and Devices - SBMicro 2010. 2010 ;31( 1): 59-65.[citado 2024 maio 23 ] Available from: https://doi.org/10.1149/1.3474142
Vancouver
Galeti M, Rodrigues M, Collaert N, Simoen E, Claeys C, Martino JA. Analog performance of SOI nFinFETs with different TiN gate electrode thickness [Internet]. Microelectronics Technology and Devices - SBMicro 2010. 2010 ;31( 1): 59-65.[citado 2024 maio 23 ] Available from: https://doi.org/10.1149/1.3474142
Trabalho de evento
Impact of TiN metal gate thickness and the HsSiO nitridation on MuGFETs electrical performance (2009)
Rodrigues, M; Mercha, A.; Simoen, Eddy ; Collaert, Nadine ; Claeys, Cor ; Martino, João Antonio
Source: Proceedings: ULIS 2009. Conference titles: International Conference on Ultimate Integration on Silicon. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
RODRIGUES, M et al. Impact of TiN metal gate thickness and the HsSiO nitridation on MuGFETs electrical performance. 2009, Anais.. New York: IEEE, 2009. . Acesso em: 23 maio 2024.
APA
Rodrigues, M., Mercha, A., Simoen, E., Collaert, N., Claeys, C., & Martino, J. A. (2009). Impact of TiN metal gate thickness and the HsSiO nitridation on MuGFETs electrical performance. In Proceedings: ULIS 2009. New York: IEEE.
NLM
Rodrigues M, Mercha A, Simoen E, Collaert N, Claeys C, Martino JA. Impact of TiN metal gate thickness and the HsSiO nitridation on MuGFETs electrical performance. Proceedings: ULIS 2009. 2009 ;[citado 2024 maio 23 ]
Vancouver
Rodrigues M, Mercha A, Simoen E, Collaert N, Claeys C, Martino JA. Impact of TiN metal gate thickness and the HsSiO nitridation on MuGFETs electrical performance. Proceedings: ULIS 2009. 2009 ;[citado 2024 maio 23 ]
Trabalho de evento
Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs (2008)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Simoen, Eddy ; Rooyackers, Rita; Collaert, Nadine ; Claeys, Cor
Source: SBMICRO 2008: Anais. Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs. 2008, Anais.. Pennington: The Electrochemical Society, 2008. . Acesso em: 23 maio 2024.
APA
Pavanello, M. A., Martino, J. A., Simoen, E., Rooyackers, R., Collaert, N., & Claeys, C. (2008). Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs. In SBMICRO 2008: Anais. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Martino JA, Simoen E, Rooyackers R, Collaert N, Claeys C. Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs. SBMICRO 2008: Anais. 2008 ;[citado 2024 maio 23 ]
Vancouver
Pavanello MA, Martino JA, Simoen E, Rooyackers R, Collaert N, Claeys C. Influence of fin width on the intrinsic voltage gain of standard and strained triple-gate nFinFETs. SBMICRO 2008: Anais. 2008 ;[citado 2024 maio 23 ]

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